e51: CPU.RiscV64 @ sysbus
    cpuType: "rv64imac_zicsr_zifencei"
    hartId: 0
    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
    timeProvider: clint
    CyclesPerInstruction: 8
    init:
        RegisterCustomCSR "BPM" 0x7C0 Machine

u54_1: CPU.RiscV64 @ sysbus
    cpuType: "rv64gc_zicsr_zifencei"
    hartId: 1
    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
    timeProvider: clint
    CyclesPerInstruction: 8
    allowUnalignedAccesses: true
    init:
        RegisterCustomCSR "BPM" 0x7C0 Machine

u54_2: CPU.RiscV64 @ sysbus
    cpuType: "rv64gc_zicsr_zifencei"
    hartId: 2
    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
    timeProvider: clint
    CyclesPerInstruction: 8
    allowUnalignedAccesses: true
    init:
        RegisterCustomCSR "BPM" 0x7C0 Machine

u54_3: CPU.RiscV64 @ sysbus
    cpuType: "rv64gc_zicsr_zifencei"
    hartId: 3
    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
    timeProvider: clint
    CyclesPerInstruction: 8
    allowUnalignedAccesses: true
    init:
        RegisterCustomCSR "BPM" 0x7C0 Machine

u54_4: CPU.RiscV64 @ sysbus
    cpuType: "rv64gc_zicsr_zifencei"
    hartId: 4
    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
    timeProvider: clint
    CyclesPerInstruction: 8
    allowUnalignedAccesses: true
    init:
        RegisterCustomCSR "BPM" 0x7C0 Machine

clint: IRQControllers.CoreLevelInterruptor  @ sysbus 0x2000000
    frequency: 1000000
    numberOfTargets: 5
    [0, 1] -> e51@[3, 7]
    [2, 3] -> u54_1@[3, 7]
    [4, 5] -> u54_2@[3, 7]
    [6, 7] -> u54_3@[3, 7]
    [8, 9] -> u54_4@[3, 7]

pdma: DMA.MPFS_PDMA @ sysbus 0x3000000
    [0-7] -> plic@[5-12]

plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0xc000000
    // E51: only machine mode interrupt
    0 -> e51@11
    // No user mode or hypervisor mode interrupts
    [1,2] -> u54_1@[11,9]
    [3,4] -> u54_2@[11,9]
    [5,6] -> u54_3@[11,9]
    [7,8] -> u54_4@[11,9]
    numberOfSources: 186
    numberOfContexts: 9
    prioritiesEnabled : false

mmuart0: UART.NS16550 @ sysbus 0x20000000
    wideRegisters: true
    IRQ -> plic@90 | e51@27

mmuart1: UART.NS16550 @ sysbus 0x20100000
    wideRegisters: true
    IRQ -> plic@91 | u54_1@27

mmuart2: UART.NS16550 @ sysbus 0x20102000
    wideRegisters: true
    IRQ -> plic@92 | u54_2@27

mmuart3: UART.NS16550 @ sysbus 0x20104000
    wideRegisters: true
    IRQ -> plic@93 | u54_3@27

mmuart4: UART.NS16550 @ sysbus 0x20106000
    wideRegisters: true
    IRQ -> plic@94 | u54_4@27

mmc: SD.MPFS_SDController @ sysbus 0x20008000
    IRQ -> plic@88
    WakeupIRQ -> plic@89

spi0: SPI.MPFS_SPI @ sysbus 0x20108000
    IRQ -> plic@54

spi1: SPI.MPFS_SPI @ sysbus 0x20109000
    IRQ -> plic@55

i2c0: I2C.MPFS_I2C @ sysbus 0x2010A000
    IRQ -> plic@58

i2c1: I2C.MPFS_I2C @ sysbus 0x2010B000
    IRQ -> plic@61

can0: CAN.MPFS_CAN @ sysbus 0x2010C000
    IRQ -> plic@56

can1: CAN.MPFS_CAN @ sysbus 0x2010D000
    IRQ -> plic@57

mac0: Network.CadenceGEM @ { sysbus 0x20110000; sysbus 0x28110000 }
    IRQ -> plic@64 | u54_1@24 | u54_2@24

mac1: Network.CadenceGEM @ { sysbus 0x20112000; sysbus 0x28112000 }
    IRQ -> plic@70 | u54_3@24 | u54_4@24

phy: Network.EthernetPhysicalLayer @ {
        // this is a slight hack to enable testing on multiple physical configurations with a single repl
        mac0 3;
        mac0 4;
        mac0 16;
        mac1 3;
        mac1 4;
        mac1 9;
        mac1 16
    }
    BasicStatus: 0x62A4
    Id1: 0x0007
    Id2: 0x0660
    AutoNegotiationAdvertisement: 0x1e1
    AutoNegotiationLinkPartnerBasePageAbility: 0x1e1
    MasterSlaveControl: 0x300
    MasterSlaveStatus: 0x3000

gpio0: GPIOPort.MPFS_GPIO @ sysbus 0x20120000
    [0-13] -> plic@[13-26]
    IRQ -> plic@51

gpio1: GPIOPort.MPFS_GPIO @ sysbus 0x20121000
    [0-23] -> plic@[27-50]
    IRQ -> plic@52

gpio2: GPIOPort.MPFS_GPIO @ sysbus 0x20122000
    [0-31] -> plic@[13-44]
    IRQ -> plic@53

wdog0: Timers.MPFS_Watchdog @ sysbus 0x20001000
    frequency: 156250 //this value is estimated from the comments in the code
    RefreshEnable -> plic@100 | e51@26
    Trigger -> plic@105 | e51@25

wdog1: Timers.MPFS_Watchdog @ sysbus 0x20101000
    frequency: 156250 //this value is estimated from the comments in the code
    RefreshEnable -> plic@101 | u54_1@26
    Trigger -> plic@106 | u54_1@25 | e51@24

wdog2: Timers.MPFS_Watchdog @ sysbus 0x20103000
    frequency: 156250 //this value is estimated from the comments in the code
    RefreshEnable -> plic@102 | u54_2@26
    Trigger -> plic@107 | u54_2@25 | e51@23

wdog3: Timers.MPFS_Watchdog @ sysbus 0x20105000
    frequency: 156250 //this value is estimated from the comments in the code
    RefreshEnable -> plic@103 | u54_3@26
    Trigger -> plic@108 | u54_3@25 | e51@22

wdog4: Timers.MPFS_Watchdog @ sysbus 0x20107000
    frequency: 156250 //this value is estimated from the comments in the code
    RefreshEnable -> plic@104 | u54_4@26
    Trigger -> plic@109 | u54_4@25 | e51@21

rtc: Timers.MPFS_RTC @ sysbus 0x20124000
    WakeupIRQ -> plic@80
    MatchIRQ -> plic@81

mstimer: Timers.MPFS_Timer @ sysbus 0x20125000
    Timer1IRQ -> plic@82
    Timer2IRQ -> plic@83

envmCfg: MTD.MPFS_eNVM @ sysbus 0x20200000
    memory: envmData
    IRQ -> plic@84

envmData: Memory.MappedMemory @ sysbus 0x20220000
    size: 0x20000

usb: USB.MPFS_USB @ sysbus 0x20201000
    DmaIRQ -> plic@86
    MainIRQ -> plic@87

l2Lim: Memory.MappedMemory @ sysbus 0x08000000
    size: 0x02000000

l2ZeroDevice: Memory.MappedMemory @ sysbus 0x0A000000
    size: 0x02000000

e51DTim: Memory.MappedMemory @ sysbus 0x01000000
    size: 0x2000

e51Hart0ITim: Memory.MappedMemory @ sysbus 0x01800000
    size: 0x2000

u54Hart1ITim: Memory.MappedMemory @ sysbus 0x01808000
    size: 0x7000

u54Hart2ITim: Memory.MappedMemory @ sysbus 0x01810000
    size: 0x7000

u54Hart3ITim: Memory.MappedMemory @ sysbus 0x01818000
    size: 0x7000

u54Hart4ITim: Memory.MappedMemory @ sysbus 0x01820000
    size: 0x7000

// The exact DDR Memory Partition depends on the amount of physically connected DDR memory.
// Both BeagleV-Fire and PolarFire SoC Icicle Kit based on this soc are equipped with 2GB,
// so we put it here divided into ddr and ddr2 parts as a sane default.
// Override size at a board level if different configuration is expected.
ddr: Memory.MappedMemory @ {
        sysbus 0x80000000;
        sysbus <0xC0000000, +0x10000000>;
        sysbus <0xD0000000, +0x10000000>;
        sysbus 0x1000000000;
        sysbus 0x1400000000;
        sysbus 0x1800000000
    }
    size: 0x40000000

ddr2: Memory.MappedMemory @ {
        sysbus 0x1040000000;
        sysbus 0x1440000000;
        sysbus 0x1840000000
    }
    size: 0x40000000

mem_bootloader: Memory.MappedMemory @ sysbus 0x0
    size: 0x100000

pcie0: PCI.MPFS_PCIe @ sysbus 0x53004000

pcie1: PCI.MPFS_PCIe @ {
        sysbus 0x53008000;
        sysbus new Bus.BusMultiRegistration { address: 0x60000000; size: 0x20000000; region: "ecam" }
    }

pcieRC0: PCI.PCIeRootComplex @ pcie0 0
    parent: pcie1

pcieRC1: PCI.PCIeRootComplex @ pcie1 0
    parent: pcie1

pcieMem: PCI.PCIeMemory  @ pcie1 1
    size: 0x20000
    parent: pcie1

mailbox: Memory.ArrayMemory @ sysbus 0x37020800
    size: 0x800

athena: Miscellaneous.Crypto.AthenaX5200 @ sysbus 0x22000000

ioscb: Python.PythonPeripheral @ sysbus 0x37080000
    size: 0x1f7ffff
    script: '''request.Value = 0xFFFFFFFF'''

// There are 8 BootRom registers covering range from 0x20003120 to 0x2000313F,
// but because of Renode's memory alignment limitations they are mapped as a single memory
sysregScbBootRom: Memory.MappedMemory @ sysbus 0x20003000
    size: 0x1000

DDR_CTRLR: Miscellaneous.MPFS_DDRMock @ sysbus 0x3e001000
DDR_PHY: Miscellaneous.MPFS_DDRMock @ sysbus 0x20007000
SCB_DDR_PLL: Miscellaneous.MPFS_DDRMock @ sysbus 0x3e010000
DDRCFG: Miscellaneous.MPFS_DDRMock @ sysbus 0x20080000

CacheConfig_WayEnable: Python.PythonPeripheral @ sysbus 0x02010008
    size: 0x8
    initable: true
    script: '''
if request.IsInit:
    reg = 0x0
elif request.IsRead:
    request.Value = reg
elif request.IsWrite:
    reg = request.Value
'''

TopSystemRegisters: Miscellaneous.MPFS_Sysreg @ sysbus 0x20002000

sysbus:
    init:
        // DDR Memory Address Space is tagged below.
        // The exact DDR Memory Partition depends on the amount of physically connected DDR memory.
        Tag <0x80000000 0x40000000> "DDR Cached 1GB"
        Tag <0x1000000000 0x400000000> "DDR Cached 16GB"
        Tag <0xC0000000 0x10000000> "DDR Non-Cached 256MB"
        Tag <0xD0000000 0x10000000> "DDR Non-Cached WCB 256MB"
        Tag <0x1400000000 0x400000000> "DDR Non-Cached 16GB"
        Tag <0x1800000000 0x400000000> "DDR Non-Cached WCB 16GB"
        SilenceRange <0x02010010, 0x02010FFF> # "Cache controller"
        SilenceRange <0x01700000, 0x01704FFF> # Bus error units
        Tag <0x37080000, 0x38FFFFFF> "IOSCB" 0xFFFFFFFF
        Tag <0x20005000, 0x20005FFF> "MPU Config"

        Tag <0x20007000, 0x20007FFF> "CFG_DDR_SGMII_PHY"
        Tag <0x20007208, 0x2000720B> "IOC_REG1" 0xFF
        Tag <0x20007814, 0x20007817> "TRAINING_STATUS" 0xFF
        Tag <0x20007808, 0x2000780B> "LANE_SELECT" 0
        Tag <0x2000781C, 0x2000781F> "GT_ERR_COMB" 0
        Tag <0x20007834, 0x20007837> "DQ_DQS_ERR_DONE" 0x8
        Tag <0x2000784C, 0x2000784F> "DQDQS_WINDOW" 0x8
        Tag <0x20007C20, 0x20007C23> "PVT_STAT" 0x4040

        Tag <0x20080000, 0x2009FFFF> "DDRCFG"
        Tag <0x20084428, 0x2008442B> "CSR_APB_MT_DONE_ACK" 0x1
        Tag <0x20090034, 0x20090037> "CSR_APB_STAT_DFI_INIT_COMPLETE" 0x1
        Tag <0x20090038, 0x2009003B> "CSR_APB_STAT_DFI_TRAINING_COMPLETE" 0x1
        Tag <0x3E040008, 0x3E04000B> "IOSCB_IO_CALIB_DDR:IOC_REG1" 0xFF
